This invention generally relates to a method for etching semiconductor features and more particularly to a method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
For example, fabrication of a complementary metal-oxide-semiconductor (CMOS) integrated circuit involves numerous processing steps. CMOS technology uses metal oxide semiconductor field effect transistors (MOSFET) to form, for example, logic elements. In forming a MOSFET, a gate structure is central to the operation of the device. For example, a gate dielectric (gate oxide) of for example, silicon dioxide, is formed over a semiconductor substrate of, for example, silicon which is doped with either n-type or p-type impurities. A gate conductor is then formed over the gate dielectric, and dopant impurities are introduced into the substrate to form a source and drain.
A driving trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. Many modern day processes employ features, such as gate conductors, which have less than 0.5 micron critical dimension (CD). For example the gate length is the smallest feature of the MOSFET patterned by lithography and etching. Optical lithography has been able to provide generations of feature size reduction by using wavelengths a short as 193 nm for sub 0.5 micron lithography. Future feature size reductions by x-ray, extreme UV, and electron beam may prove costly and difficult. Gate length and gate oxide thickness are exemplary critical dimensions in gate structure manufacturing. Gate length is usually determined by the lithography and etching capability of manufacturing techniques. As such, sub-lithographic wet etching methods or combinations of processes including lithography, dry etching and wet etching, present attractive alternatives as critical dimensions are reduced.
In semiconductor device fabrication, polysilicon and silicon dioxide are commonly used to form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO2 layer has also decreased to maintain the same capacitance between the gate and channel regions. A thickness of the gate oxide layer of less than 2 nanometers (nm) is expected in the future.
For example, referring to FIG. 1, fabrication of a CMOS transistor including a gate structure 10 begins by lightly doping a single crystal silicon substrate either n-type or p-type. The specific area where the transistor will be formed is then electrically isolated from other areas on the substrate using various isolation structures. In modern fabrication technologies, the isolation structures may include, for example, shallow trenches (not shown) in the substrate filled with dielectric oxide which acts as an insulator. A gate dielectric (gate oxide) layer is then formed by oxidizing the silicon substrate. Oxidation is typically performed by thermal oxidation a rapid-thermal-anneal (xe2x80x9cRTAxe2x80x9d) process. A layer of polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) is then deposited over the gate dielectric.
Typically, one or more layers of hard mask material such as silicon nitride or silicon oxynitride are formed over the polysilicon prior to patterning and etching the gate structure. In addition, a dielectric anti-reflective coating of for example, silicon oxynitride may be formed over the hard mask to reduce undesired light reflections from the hard mask which serve to expose undesired areas in an overlying photoresist layer used to pattern the etching area to form the gate structure.
The polysilicon may be rendered conductive by doping it with ions from an implanter or using a thermally activated diffusion process. The gate structure is then patterned by using a photolithographic process to pattern the hard mask material followed by exposure, development, and etching. The gate structure is then etched to form the gate structure 10 shown in FIG. 1 including gate oxide 12, gate conductor 14, hard mask layer 16. Subsequently, source and drain regions are formed by doping the area on either side of the gate structure, for example source region 18A and drain region 20A, via ion implantation, with a dosage n-type or p-type dopant. More heavily doped regions may later be formed over regions 18B and 20B by forming silicon dioxide spacers (not shown) over regions 18A and 20A followed by a heavier doping dosage. If the source and drain regions are doped n-type, the transistor is referred to as NMOS, and if the source and drain regions are doped p-type, the transistor is referred to as PMOS. A channel region 22 between the source and the drain is protected from the implant species by the gate structure. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor is activated.
As semiconductor feature sizes decrease, for example, the width of a gate structure, more sophisticated photolithography techniques have been required to pattern etching masks for anisotropically plasma etching smaller semiconductor features such as gate structures while maintaining acceptable critical dimension control. As a result, the associated high costs of photolithographic patterning steps to form device sizes having, for example, device features less than 0.1 microns has been a concern in the semiconductor manufacturing art.
Wet etch techniques on the other hand, while demonstrating a high selectively for one material relative to other materials, are generally isotropic, etching at similar rates in all directions, making control of critical dimension variations of semiconductor features over a semiconductor wafer surface (CD bias) more difficult. Wet etch chemistries, however, have been found to be especially suitable for blanket etches of polysilicon, oxides, and metal nitrides. For example, hot phosphoric acid has high selectivity for metal nitrides, for example, silicon nitride and silicon oxynitride, however the hot temperatures (about 150xc2x0 C.) required of the phosphoric acid have restricted its use to wet bench techniques where the target etch surface is typically immersed in the hot phosphoric acid with mechanical agitation. In addition to the added cost due to the complexity of wet bench apparatus required for safety and other reasons, such techniques have proven unable to achieve the critical dimension control required for present semiconductor feature sizes.
There is therefore a need in the semiconductor processing art to develop wet etching methods that are economically feasible and that are able to achieve acceptable critical dimension control as device feature sizes diminish.
It is therefore an object of the invention to develop wet etching methods that are economically feasible and that are able to achieve acceptable critical dimension control as device feature sizes diminish while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control.
In one embodiment of the present invention, the method includes providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.